
IDT70V7319S
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs) (1,6)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
An
INTERNAL (3)
ADDRESS
An (5)
An + 1
An + 2
An + 3
An + 4
t SAD t HAD
ADS
t SCN t HCN
CNTEN
t SD t HD
DATA IN
Dn
Dn + 1
Dn + 1
Dn + 2
Dn + 3
Dn + 4
WRITE
EXTERNAL
ADDRESS
WRITE WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
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Timing Waveform o f Counter Repeat for Flow Through Mode (2,6,7)
t CYC2
CLK
t SA t HA
ADDRESS
An
INTERNAL (3)
ADDRESS
An
An+1
An+2
An+2
An
An+1
An+2
An+2
t SAD t HAD
ADS
t SW t HW
R/ W
t SCN t HCN
CNTEN
REPEAT
(4)
t SRPT t HRPT
t SD t HD
DATA IN
D 0
D 1
D 2
D 3
t CD1
DATA OUT
An
An+1
An+2
An+2
,
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
NOTES:
1. CE 0 , UB / LB , and R/ W = V IL ; CE 1 and REPEAT = V IH .
2. CE 0 , UB / LB = V IL ; CE 1 = V IH .
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3. The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.
7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
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